Setup:
- PLL generated from MageWizard with thre clockes
- PLL Reconfig Megafunction
- 2 ROM generated from Megawizard
- State machine to start the PLL Reconfig Megafunction, based on the example in the user guide
- FPGA: Cyclone3, 40 (120 on eval board), 780 pins packet, speed grade 8 (slowest)
All VHDL files are linked correctly. To run the configuration I use a 72 MHz clock egnerated from 125 MHz clock in a PLL. In this case the PLL stop working.
Then I made a design with the eval board, just to get the PLL reconfig work. In this case I only made it work when I used the clock from 50 MHZ onboard oszilator. If I used a clock from a PLL or a external clock with another frequency it doesn't work.
@mazel: Waat do you defines as "waiting enough time" between the ROM reading and the scan write. I'm waiting one cycle after the busy flag went low. Shall I wait longer ?
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