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Altera_Forum's avatar
Altera_Forum
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13 years ago

PLL "must be fed by an I/O node"

Hello All,

I'm trying to port my design over from X where I use a PLL(DLL) to generate a secondary clock that is slightly advanced so when used on registered outputs produces transitions in phase with the internal source clock.

It is all about the design being aware of when the output pins are actually toggling - and compensating for the temperature/voltage/process changes in the IO pad(s). The compensated clock from the PLL can then be used to capture the returning data. (Yes from DDR.) I can't use the 'proper' DQS capture way as I'm running the DDR too slowly: ~80MHz for an emulation system.

So I looked at the External Feedback Mode with a bidirectional pad to the Stratix IV 'PLL_L3_FB_CLKOUT0p' pad using the fbout and fbin on the PLL.

It all synthesized well and progressed in the fitter until it reported that the PLL "must be fed by an I/O node -- PLL is in the zero delay buffer or external feedback mode"

Unfortunately, I need to feed this circuit from another PLL. Does anyone know if it is possible to get around the external IO requirement?

Regards,

++Simon

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Simon,

    Not sure if you're still working on this but you could use a DDR output to drive the clock. If you use the ALTDDIO_OUT megafunction, you can drive one input high and the other low, clocking it with the clock you'd like to drive out. This is placed in the output register near the pin just like the data and should tighten up their alignment. Since they'll be almost exactly aligned, perhaps you can reverse the clock and receive it on the falling edge.

    If you're using X, not sure how familiar you are with A. If you find that your data is not being placed in the output register, use the Fast Output Register assignment.

    Hope this helps,

    Scott
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Scott,

    Many thanks for your reply, I am just revisiting this as the PLL solution I had come up with does not seem to work.

    Yes, I am using the ALTDDIO_OUT 'trick'. This should give the shortest and most deterministic clock->output for all pads on that clock. I'm also inverting it like you suggested, this has worked for me very well in the past.

    Temporarily I am trying to manually compensate for the output delay using a PLL with a fixed phase shift so that the clock on the pads matches the internal clock, this should be good enough to get me going.

    Once I get Quartus II v12 installed I will try again to get the PLL feedback to automatically adjust for this. I am having more difficulty than I should be having with this and the documentation is certainly confusing.

    Regards,

    ++Simon
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Simon,

    Just to clarify, it sounds like you'd like a clock output to your DDR device with a phase shift that automatically tracks the data output pins. Since you're trying to compensate for variation at the I/O pin, wouldn't that require an external feedback?

    Would source synchronous mode work for you? One clock driving I/O registers and core logic and a delayed clock output to the DDR device. Sounds like what you're trying now but it might help with the timing of the of the data at the pins.

    Regards,

    Scott
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Scott,

    My solution uses the PLL's external feedback pin (PLL_L3_FB_CLKOUT0p). I set it up as an always enabled bidirectional pad with DDR output and combinatorial input back to the feedback pin of the PLL.

    The goal is: To have signals driven on the board be in phase with the internal clock (c0).

    To achieve this I need a secondary clock (c1) which is slightly advanced on c0 (The amount is the pad delay.)

    When c1 is used to clock outputs the signals on the board are in phase with c0.

    The first problem I encountered was when I used 'external feedback' and the fitter complained that the input clock c0 "must be fed by an I/O node"

    I had some luck with zero-delay-buffer mode (it went through fitting) but I don't think that it actually compensated for the pad delay. It didn't in the simulator.

    Thanks for the help with this. I've just got Quartus 12 installed to see if there is any difference.

    Regards,

    ++Simon