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Altera_Forum
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13 years ago

PLL "must be fed by an I/O node"

Hello All, I'm trying to port my design over from X where I use a PLL(DLL) to generate a secondary clock that is slightly advanced so when used on registered outputs produces transitions in pha...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Hi Scott,

Many thanks for your reply, I am just revisiting this as the PLL solution I had come up with does not seem to work.

Yes, I am using the ALTDDIO_OUT 'trick'. This should give the shortest and most deterministic clock->output for all pads on that clock. I'm also inverting it like you suggested, this has worked for me very well in the past.

Temporarily I am trying to manually compensate for the output delay using a PLL with a fixed phase shift so that the clock on the pads matches the internal clock, this should be good enough to get me going.

Once I get Quartus II v12 installed I will try again to get the PLL feedback to automatically adjust for this. I am having more difficulty than I should be having with this and the documentation is certainly confusing.

Regards,

++Simon