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Honored Contributor
Honored ContributorPLL "must be fed by an I/O node"
Hello All, I'm trying to port my design over from X where I use a PLL(DLL) to generate a secondary clock that is slightly advanced so when used on registered outputs produces transitions in pha...
Altera_ForumHonored Contributor
Honored ContributorHi Simon,
Just to clarify, it sounds like you'd like a clock output to your DDR device with a phase shift that automatically tracks the data output pins. Since you're trying to compensate for variation at the I/O pin, wouldn't that require an external feedback? Would source synchronous mode work for you? One clock driving I/O registers and core logic and a delayed clock output to the DDR device. Sounds like what you're trying now but it might help with the timing of the of the data at the pins. Regards, Scott
