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Altera_Forum
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14 years ago

PLL "must be fed by an I/O node"

Hello All, I'm trying to port my design over from X where I use a PLL(DLL) to generate a secondary clock that is slightly advanced so when used on registered outputs produces transitions in pha...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi Scott,

My solution uses the PLL's external feedback pin (PLL_L3_FB_CLKOUT0p). I set it up as an always enabled bidirectional pad with DDR output and combinatorial input back to the feedback pin of the PLL.

The goal is: To have signals driven on the board be in phase with the internal clock (c0).

To achieve this I need a secondary clock (c1) which is slightly advanced on c0 (The amount is the pad delay.)

When c1 is used to clock outputs the signals on the board are in phase with c0.

The first problem I encountered was when I used 'external feedback' and the fitter complained that the input clock c0 "must be fed by an I/O node"

I had some luck with zero-delay-buffer mode (it went through fitting) but I don't think that it actually compensated for the pad delay. It didn't in the simulator.

Thanks for the help with this. I've just got Quartus 12 installed to see if there is any difference.

Regards,

++Simon