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Altera_Forum
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13 years ago

PLL "must be fed by an I/O node"

Hello All, I'm trying to port my design over from X where I use a PLL(DLL) to generate a secondary clock that is slightly advanced so when used on registered outputs produces transitions in pha...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Hi Simon,

Not sure if you're still working on this but you could use a DDR output to drive the clock. If you use the ALTDDIO_OUT megafunction, you can drive one input high and the other low, clocking it with the clock you'd like to drive out. This is placed in the output register near the pin just like the data and should tighten up their alignment. Since they'll be almost exactly aligned, perhaps you can reverse the clock and receive it on the falling edge.

If you're using X, not sure how familiar you are with A. If you find that your data is not being placed in the output register, use the Fast Output Register assignment.

Hope this helps,

Scott