[PLL IP] missing generated clock

Hi All,

I'm receiving the following message during PLL compilation:

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Warning (332056): Node: i_pmu|i_alt_pll|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 12.500

--- Quote End ---

So, what's the problem? Actually the PLL is configured for an input clock of 80MHz and two output clocks 10MHz and 20MHz.

I tried to re-create the IP, but received the same results.

How to fix it?

Thank you