New ContributorI am trying to implement the design example of JESD204B on the Apollo Agilex 7 board and using AFE79 EVM; these boards are connected with the help of FMC.
I need help with pin assignments, like mgmt_clk,refclk_core,refclk_xcvr, etc.; how do I assign pins for these(all pins should match for the Agilex FPGA and AFE79 EVM?
and how SPI module pin should be assigned?
Occasional ContributorHi,
Please share details about Apollo Agilex 7, Device ID/OPN number?
Are you using Quartus Prime Pro?
Regards,
Harsh M
New ContributorHi Harsh,
Intel® Agilex® SoC FPGA : AGFB014R24B1E1V/AGFB014R24B2E2V
Product Line: AGFB014R24B
Device ID (32 bits): Version (4 bits): 1100
Part Number (16 Bits): 0011 0100 0001 1010
Yes I am using Quartus Prime Pro software version 24.1
Occasional ContributorHi,
You can refer the following:
I need help with pin assignments, like mgmt_clk,refclk_core,refclk_xcvr, etc.; how do I assign pins for these(all pins should match for the Agilex FPGA and AFE79 EVM?
1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview (intel.com)
You can refer this if you get error at Fitter stage in Quartus. This will give you a better understanding for clocking scheme for Agilex 7.
how SPI module pin should be assigned?
1.7.11. HPS SPI Pins (intel.com)
Regards,
Harsh M
