Honored ContributorWith all the applications for SERDES and 1000BASE products, I would think that there might be a device which I could program that will perform the 100BASE-TX and/or 100BASE-FX function that I am looking for.
Does anybody know if there is an FPGA device and IP which might allow me to replace my PHY device?
Honored ContributorIf you took a detailed look at the ethernet physical layer of the said network types http://standards.ieee.org/getieee802/802.3.html, you'll recognize, that each uses specific features, that are not provided by available fast serial interfaces of FPGA.
P.S.: Newer Altera FPGA with Gigabit interface are providing a GIGE (Gigabit Ethernet) protocol. As far as I understand, it's (almost ?) equivalent to IEEE 1000BASECX (short-haul copper) that uses unidirectional twisted pairs. Standard 1000BASE-T uses 4 twisted pairs at 250 Mbit each, bidirectionally operated through hybrids.Honored ContributorSome of the FPGA devices offer the ability to use fewer byte lanes and also make available an intermediate exit place for the extracted data. I need clock extraction and logic to do the optional scrambler and I do not know if it exists in the world of programmable logic devices.
I am running into an obsolescence problem with my PHY devices which like to run an MII interface using 5B symbol modes. If I could replace them with programmable logic, that would solve the problem.Honored ContributorI expect most problems with the analog signal features of the PHY.
Honored ContributorCould you tell us what PHY device you are having obsolescence problems with? That would make it much easier to suggest solutions :-)
Honored ContributorAM79C874 Running in 5B symbol mode.
The MII interface uses 5-bits to allow the CMD-n commands to be sent. Our protocol is a ring topology that passes a baton using CMD commands. Our state machine (MAC) layer device handles the 4B/5B conversions. I was hoping that the SERDES interfaces could be dissected enough to allow our customizing of a single channel to get the 125Mb data rate and also allow us to insert our own 4B/5B conversion module. Sorry for taking so long to reply and thanks for your help!Honored ContributorAltera transceivers will not perform hard clock-data recovery for data rates below I believe 640Mbps or something like that. You could perform oversampling or soft-CDR but you wouldn't be able to use the recovered clock to re-transmit. You could use an external clock cleaner (like maybe an Si5234)
http://www.silabs.com/products/clocksoscillators/clocks/pages/any-ratejitterattenuatingclockmultipliers.aspx to restore the true clock from your soft-CDR clock. You'd want to provide the clock cleaner with a lower-frequency divided-down version of the clock in order to keep the jitter within spec. This also means you'd have to perform some buffering. I think you could make it work and honestly I think it would be fun but you'd have to do some experimentation. Seems like a Cyclone IV GX would be a good fit for something like this. JakeHonored ContributorIf you could solve the CDR problem, you still don't have any of the analog PHY features required for 100BASE-TX or 10BASE-T.
Honored ContributorIt seems this is the main issue is the capability of sending/receiving the CMD-n character.
Does anybody know if the SMII or SGMII protocols support the transmission of special characters? If so, then perhaps a PHY with SMII or SGMII interface could be used in conjunction with an FPGA. JakeHonored ContributorWe have had an MII interface to our gate arrays for some time now. We have a lot of gate arrays that we were not interested in changing the interface upon.
I thought that SERDES in the FPGA devices ran as low as 200MHz when the number of channels is maxed out. Clock extraction is the main problem with the FPGAs. I have been trying to figure out whether any devices had the analog components specifically applied to them for the special clock extraction requirements. I was assuming that SERDES wants a similar clock extraction too. Obviously, the FPGA solution would be more expensive than a typical PHY chip. If combined with my other MAC logic, it might become a more equitable process. That is why I am looking for it!
