PHY Layer FPGA

Altera transceivers will not perform hard clock-data recovery for data rates below I believe 640Mbps or something like that. You could perform oversampling or soft-CDR but you wouldn't be able to use the recovered clock to re-transmit. You could use an external clock cleaner (like maybe an Si5234)

http://www.silabs.com/products/clocksoscillators/clocks/pages/any-ratejitterattenuatingclockmultipliers.aspx

to restore the true clock from your soft-CDR clock. You'd want to provide the clock cleaner with a lower-frequency divided-down version of the clock in order to keep the jitter within spec. This also means you'd have to perform some buffering.

I think you could make it work and honestly I think it would be fun but you'd have to do some experimentation. Seems like a Cyclone IV GX would be a good fit for something like this.

Jake