PHY Layer FPGA

We have had an MII interface to our gate arrays for some time now. We have a lot of gate arrays that we were not interested in changing the interface upon.

I thought that SERDES in the FPGA devices ran as low as 200MHz when the number of channels is maxed out.

Clock extraction is the main problem with the FPGAs. I have been trying to figure out whether any devices had the analog components specifically applied to them for the special clock extraction requirements. I was assuming that SERDES wants a similar clock extraction too.

Obviously, the FPGA solution would be more expensive than a typical PHY chip. If combined with my other MAC logic, it might become a more equitable process. That is why I am looking for it!