Hi VYoung
All the intel families support the feature you are looking for.
You could look for the PLL Soft Core IP which are supported for all the Intel FPGA devices.
There are 2 types of PLL cores that are available and are supported in different FPGA families.
You could look into the "supported devices" in the documents below:
https://www.intel.com/content/www/us/en/docs/programmable/683285/18-1/core-user-guide.html
https://www.intel.com/content/www/us/en/docs/programmable/683359/17-0/altera-phase-locked-loop-ip-core-user-guide.html
In the Soft IP you could select the number of clock signals, different frequency for each signals and also adjust the phase difference.
Regards
Jingyang, Teh