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Altera_Forum's avatar
Altera_Forum
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16 years ago

phase problem about transceiver of stratix ii GX

Hi, I need help for a problem

I use transceiver of stratix ii GX for high speed output, and need four channels. The output of transmitters is right, but the phase are different for different channels, which i can understand and handle. But my problem is that when I reboot the FPGA(power off then power on), the phase relationship between channels change.

It looks like everytime I reboot the FPGA, the phase relationship is random.

I can't understand the reason for that.

So can anyone give me some help about the reason and method to solve this problem. I just need to make the phase relationship between channels fixed rather than random.

Thank you

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The behavior is most likely due to the phase compensation FIFO inside the transceiver. They come out of reset at different times.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for your reply. Is there any way to solve this problem, how can I make the FIFO reset at the same time? or I can't...

    Thanks again
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I retract my previous statement. I did not pay close enough attention. You are saying that the individual bits of the serial output are not phase aligned. Is that correct? If so, the behavior is likely caused by the serializer itself.

    The only way I can think of to remove the skew is to operate the transmitters in bonded mode. Bonded mode is intended to specifically remove that channel-to-channel TX skew. However this imposes certain restrictions which you may not be able to live with in your design.

    What mode are you currently operating the transceiver in? Are all of your channels located within the same Quad?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I instantiated five transmitter channels using alt2gxb module. Four of them are in the same quad.

    I don't need to remove the phase difference between channels, I just want to get a fixed difference. Now the situation is like this, say the time difference between the serial output of channel 1 and channel 2 is 4 ns (channel 2 delay 4 ns). if I turn off fpga and reboot it again, this time difference will change to other value, such as 2 ns, and channel 2 may be ahead this time. Every time I reboot FPGA, the time relationship between channels are different, even for the four channel in same quad.

    I can understand there are time difference for the output of channels, but I can't understand why this difference change random.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Do you reset the Transceiver (respectively release the reset) after a stable reference clock is present? I would assume this as a prerequisite to achieve predictable timing relations. It may be the case, that Stratix II doesn't provide it anyway.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I am Dr. David Pommerenk the adviser of Xu Gao, allow me to go into this conversation.

    Let me add one more piece of information.

    We are using the Altera provided Transceiver evaluation board "Stratix II GX Transceiver SI Board" Rev. D. In a deterministic device I do not see a reason why the timing should not come up the same way, every time the device is allowed to wake up from reset.

    If we know the reason, we maybe able to correct it in software.

    Please advise us on how to proceed.

    Regards,

    Dr. David Pommerenke
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You are not the first to tackle this problem. A search of the forum will reveal other similar discussions. The problem I believe is that the individual transceiver channels actually have internal reset circuitry. The serializers are coming out of reset at different (random) times. I do not believe you have access to control this.

    Protocols that require strict channel-to-channel skew requirements typically use bonding.

    It sounds like you obviously have control of the receiver as well if you're able to tolerate a fixed skew. Can you implement dynamic phase alignment at the receiver?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    we can't implement dynamic phase alignment now, but I believe it is doable.

    Thank you. Your reply is helpful, I hope I and fix this problem.

    Xu
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Here is another thread that explored the same issue

    --- Quote End ---

    It seems to suggest, that the feature to achieve a deterministic timing after a reset has been actually forgotten when designing the chip. But to be sure, I would ask Altera support.