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Altera_Forum
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11 years ago

PCIe memory access trouble about CycloneV Avalon-MM Hard IP for PCIe

Hello.

I develop a CycloneV board to communicate to external CPU by PCIe.

So, I use the Avalon-MM Cyclone V HardIP for PCIe(quartus ver13.1).

I try to read access from external CPU to FPGA by PCIe, then the 0xffff_ffff are returned at all region.

But if I embedded the signaltap without trigger(signal : RxmWaitRequest, RxmAddress, RxmWrite, RxmWriteData),some read/write access is successful.

What is the problem about this?

Please teach me how to resolve it!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi Ryusuke

    I have faced a similar problem of reading back 0xffffffff. What is worse is that I have to power cycle my board after this happens.

    I have had some success by removing the Avalon MM clock crossing bridge and simply exporting the Rxm_bar Avalon MM interface with a Clock crossing bridge. Try that. I will
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    When you read back 0xffff_ffff, what you're actually getting is -1, which indicates that the read has failed. Are you sure you have all of the wires correctly connected, and they follow the user guide?

    Also, if you just want to transfer data over PCIe, you should look at riffa.ucsd.edu