Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

PCIe memory access trouble about CycloneV Avalon-MM Hard IP for PCIe

Hello. I develop a CycloneV board to communicate to external CPU by PCIe. So, I use the Avalon-MM Cyclone V HardIP for PCIe(quartus ver13.1). I try to read access from external CPU to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Ryusuke

I have faced a similar problem of reading back 0xffffffff. What is worse is that I have to power cycle my board after this happens.

I have had some success by removing the Avalon MM clock crossing bridge and simply exporting the Rxm_bar Avalon MM interface with a Clock crossing bridge. Try that. I will