Hi, I am using PCIe gen 4 (16 lanes) (512bit/500MHz clk , payload size:512B) CORE, in Agilex device: AGFB014R24A2E2VR0, for transfer DMA writings from the FPGA to the PC’s memory. Since the rate of the ready out signal (coming from the PCIe core) toggling is not constant, a FIFO must be placed between the data source (Sensor) and the DMA, to absorb the volatility. The problem is the ready signal stays in off position for a long time (instead of toggling more homogeneously) and causes the FIFO to overflow (I'm talking about FIFO in the size of 64MB). Are you familiar with this issue ? What do you think can be done to make the ready signal not to create such long breaks, but to disperse them over time for a number of short breaks? Thanks Avi

Hi Avi, As a start, Programs that become unresponsive can be due to a myriad of reasons and might be difficult to pinpoint exactly. However, I've laid out some suggestions to help you narrow this down further. As a normal data transfer condition, FIFO buffer overflow normally does not occurs, but it can result if there is a programming error. Example transmit PBL =4, TX watermark =1, if the FIFO buffer has only one location empty, the DMA attempts to read four words from memory even though there is only one word of storage available. This results in a FIFO Buffer Overflow interrupt. The driver must ensure that the number of bytes to be transferred, as indicated in the descriptor, is a multiple of four bytes. For example, if the bytcnt register = 13, the number of bytes indicated in the descriptor must be rounded up to 16 because the length field must always be a multiple of four bytes. Please let me know if it is helpful. Regards, WeiChuan_C_Intel

Hi,We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you Regards, WeiChuan_C_Intel

First of all sorry for the delay in my response , I switched to another urgent short mission. I checked the FIFO management and found that everything is fine in terms of the reason you mentioned. Can you tell me the size of the FIFO that other developers have had to place in order to absorb the volatility of the ready signal coming from the PCIe4 core? If there is not yet enough data for gen 4 , I would happy to get an answer even for gen 3. Thanks Avi

Hi Avi, Thanks for your reply. To accommodate PCIe gen3 protocol requirements and to compensate for clock frequency differences of up to ±300 ppm between source and termination equipment, receiver channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP characters (32 bits) to keep the FIFO from becoming empty or full. It monitors the block synchronizer for a skip_found signal. If the rate match FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is nearly empty, the FIFO inserts an SKP character at the start of the next available SKP ordered set. Hope this answers your question, let me know if it is helpful. Regards, WeiChuan_C_Intel

PCIe Gen 4 16 Lanes Core in Agilex - ready out signal behave

17 Replies

Avi_V_888
New Contributor
3 years ago
????
Wincent_Altera
Regular Contributor
3 years ago
Hi Avi,

As a start, Programs that become unresponsive can be due to a myriad of reasons and might be difficult to pinpoint exactly.
However, I've laid out some suggestions to help you narrow this down further. As a normal data transfer condition, FIFO buffer overflow normally does not occurs, but it can result if there is a programming error. Example transmit PBL =4, TX watermark =1, if the FIFO buffer has only one location empty, the DMA attempts to read four words from memory even though there is only one word of storage available. This results in a FIFO Buffer Overflow interrupt.

The driver must ensure that the number of bytes to be transferred, as indicated in the descriptor, is a multiple of four bytes. For example, if the bytcnt register = 13, the number of bytes indicated in the descriptor must be rounded up to 16 because the length field must always be a multiple of four bytes.

Please let me know if it is helpful.

Regards,

WeiChuan_C_Intel
- Wincent_Altera
  Regular Contributor
  3 years ago
  Hi,
  
  We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
  
  Regards,
  
  WeiChuan_C_Intel
  - Avi_V_888
    New Contributor
    3 years ago
    First of all sorry for the delay in my response , I switched to another urgent short mission.
    
    I checked the FIFO management and found that everything is fine in terms of the reason you mentioned.
    
    Can you tell me the size of the FIFO that other developers have had to place in order to absorb the volatility of the ready signal coming from the PCIe4 core?
    
    If there is not yet enough data for gen 4 , I would happy to get an answer even for gen 3.
    
    Thanks
    
    Avi
Wincent_Altera
Regular Contributor
3 years ago
Hi,

I saw in the system, your question has been addressed in IPS.
I will set this as close, if you have any other questions in the future feel free to open a new case.

Regards,
WeiChuan_C_Intel

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PCIe Gen 4 16 Lanes Core in Agilex - ready out signal behave

17 Replies

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