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Avi_V_888's avatar
Avi_V_888
Icon for New Contributor rankNew Contributor
4 years ago

PCIe Gen 4 16 Lanes Core in Agilex - ready out signal behave

Hi, I am using PCIe gen 4 (16 lanes) (512bit/500MHz clk , payload size:512B) CORE, in Agilex device: AGFB014R24A2E2VR0, for transfer DMA writings from the FPGA to the PC’s memory. Since the rat...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


I saw in the system, your question has been addressed in IPS.

I will set this as close, if you have any other questions in the future feel free to open a new case.


Regards,

WeiChuan_C_Intel