PCIe Gen 4 16 Lanes Core in Agilex - ready out signal behave

Hi Avi,

As a start, Programs that become unresponsive can be due to a myriad of reasons and might be difficult to pinpoint exactly.
However, I've laid out some suggestions to help you narrow this down further. As a normal data transfer condition, FIFO buffer overflow normally does not occurs, but it can result if there is a programming error. Example transmit PBL =4, TX watermark =1, if the FIFO buffer has only one location empty, the DMA attempts to read four words from memory even though there is only one word of storage available. This results in a FIFO Buffer Overflow interrupt.

The driver must ensure that the number of bytes to be transferred, as indicated in the descriptor, is a multiple of four bytes. For example, if the bytcnt register = 13, the number of bytes indicated in the descriptor must be rounded up to 16 because the length field must always be a multiple of four bytes.

Please let me know if it is helpful.

Regards,

WeiChuan_C_Intel