PCIe Gen 4 16 Lanes Core in Agilex - ready out signal behave

Hi, I am using PCIe gen 4 (16 lanes) (512bit/500MHz clk , payload size:512B) CORE, in Agilex device: AGFB014R24A2E2VR0, for transfer DMA writings from the FPGA to the PC’s memory. Since the rat...