New Contributor
Regular ContributorHi Avi,
As a start, Programs that become unresponsive can be due to a myriad of reasons and might be difficult to pinpoint exactly.
However, I've laid out some suggestions to help you narrow this down further. As a normal data transfer condition, FIFO buffer overflow normally does not occurs, but it can result if there is a programming error. Example transmit PBL =4, TX watermark =1, if the FIFO buffer has only one location empty, the DMA attempts to read four words from memory even though there is only one word of storage available. This results in a FIFO Buffer Overflow interrupt.
The driver must ensure that the number of bytes to be transferred, as indicated in the descriptor, is a multiple of four bytes. For example, if the bytcnt register = 13, the number of bytes indicated in the descriptor must be rounded up to 16 because the length field must always be a multiple of four bytes.
Please let me know if it is helpful.
Regards,
WeiChuan_C_Intel
Regular ContributorHi,
We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
Regards,
WeiChuan_C_Intel
New ContributorFirst of all sorry for the delay in my response , I switched to another urgent short mission.
I checked the FIFO management and found that everything is fine in terms of the reason you mentioned.
Can you tell me the size of the FIFO that other developers have had to place in order to absorb the volatility of the ready signal coming from the PCIe4 core?
If there is not yet enough data for gen 4 , I would happy to get an answer even for gen 3.
Thanks
Avi
Regular ContributorHi Avi,
Thanks for your reply. To accommodate PCIe gen3 protocol requirements and to compensate for clock frequency differences of up to ±300 ppm between source and termination equipment, receiver channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP characters (32 bits) to keep the FIFO from becoming empty or full. It monitors the block synchronizer for a skip_found signal. If the rate match FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is nearly empty, the FIFO inserts an SKP character at the start of the next available SKP ordered set.
Hope this answers your question, let me know if it is helpful.
Regards,
WeiChuan_C_Intel
New ContributorHi,
The FIFO is to absorb the writing to the PCIe core due to the delay resulting from the processing of the ready signal coming from the PC, and not due to clock frequency differences.
The PC seems to be responding to the change in the rate of the data I am transferring to it.
Initially a change from a state of non-data transfer to a state of high rate transfer.
So, it seems that the PC does not allow ready at the desired rate, until it "realizes" that there is a high demand of data transferring as a result of which the ready signal becomes more and more valid.
Indeed, at first the FIFO overflows, and then only a small part of it is occupied.
Have you encountered a similar case?
And what can be done to cause constant readiness for a high rate of data transfer from the PC and as a results of it from the PCIe core?
Thanks
Avi
