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Honored Contributor
Honored ContributorPartial reconfiguration CRC error
I am using Stratix V FPGA, and using the partial reconfiguration feature while I got the CRC error when I do the partial reconfiguration.
FPGA is connected with CPU through PCIe interface. My software read the rbf file and write the data to a customized MMIO register in FPGA. The verilog code behind the register will transfer the data to the partial configuration control block to do the reconfiguration. When the partial reconfigured logic is simple, like just doing (data_out <= data_in + 1) things, every things are ok. I really see the functions changed in the reconfigured logic. So it means my way to use the partial configuration control block is correct. When the partial reconfigured logic is much more complex, the CRC error is reported when being reconfigured. I will tell you what have I tried: 1. Using the Partial Reconfiguration IP core from IP Catalog. a ) I try 32 bit data, 16 bit data, 8 bit data. The result is the same. 2. Using the stratixv_prblock and stratixv_crcblock primitives in my verilog code instead of using the IP core. 3. Using the JTAG programmer to do the partial reconfiguration instead of using PCIe to transfer the rbf file. All of above solutions have the same result. When the logic is simple, every things are ok. When the logic is complex, CRC error happens.
