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Altera_Forum's avatar
Altera_Forum
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14 years ago

Parallel output ADC, LVDS

Im trying to interface a TI ADS3848 ADC with my stratix-III board. The ADC uses a 14 word, parallel LVDS output ie, 28 pins.

I've read many posts on the forums having to do with getting LVDS stuff to work by using the iobuff megafunction or the lvds_TX/RX megafunctions. My question is as follows:

The ADC has 14 "2 wire" output lines. Each output consists of a positive "p" and a negative "n". The documentation for the iobuff and LVDS_TX/RX suggest the notion that quartus automatically "finds" the other polarity wire after assigning only one side. How is this possible?

Thanks

Matt

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    If the device has high-speed serializers, I would suggest using them. Just instantiate the altlvds_rx block, which will only take in a 14 bit bus, but you will assign the I/O standard to be LVDS, so a n-pair for each one gets created.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    The ADC has 14 "2 wire" output lines. Each output consists of a positive "p" and a negative "n". The documentation for the iobuff and LVDS_TX/RX suggest the notion that quartus automatically "finds" the other polarity wire after assigning only one side. How is this possible?

    --- Quote End ---

    Its not that it automatically finds them, its that the p/n pairs are hard-wired. So if your board has been routed for LVDS, then the board designer will have routed the p/n pairs as differential signals. In Quartus, once you define the p signal as being LVDS, this 'implies' the n signal of the LVDS pair, so you do not need to apply a constraint.

    Check your board schematic, and then check the pin assignments view.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Cool. It worked. Seems obvious that that is what the pin planner is supposed to do. Don't know why i thought otherwise.