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The ADC has 14 "2 wire" output lines. Each output consists of a positive "p" and a negative "n". The documentation for the iobuff and LVDS_TX/RX suggest the notion that quartus automatically "finds" the other polarity wire after assigning only one side. How is this possible?
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Its not that it automatically finds them, its that the p/n pairs are hard-wired. So if your board has been routed for LVDS, then the board designer will have routed the p/n pairs as differential signals. In Quartus, once you define the p signal as being LVDS, this 'implies' the n signal of the LVDS pair, so you do not need to apply a constraint.
Check your board schematic, and then check the pin assignments view.
Cheers,
Dave
Honored Contributor
