P-tile Debug toolkit design changes

Hi there,

I am using Intel Agilex-F series development which uses P-tile. I am trying to enable P-tile Debug took kit on the Intel reference design. I am referring to Section 7.2 of P-tile Debug tool kit.

What I want to clarify is if I want o just view the P-tile status information and not configure anything to the registers, is it as simple as below steps:

1. Enable Debug Tool kit in Pcie IP configuration

2. Connect a clock to the xcvr_reconfig_clk port of the instantiation

3. Add a pin constraint to connect the xcvr_reconfig_clk to a 100 MHz clock source.

My question is do I need to drive any other signals on the xcvr_reconfig* interface to observe the DebugTool kit?

Thanks

Binu