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Altera_Forum's avatar
Altera_Forum
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15 years ago

Output port "O" of PSEUDO_DIFF_OUT primitive... must drive only one OBUF primitive...

I'm creating a QII test project to validate an SO-DIMM design. I want to use the Quartus II created "HPC1_example_top" test bench to exercise my SO-DIMM so I created the "DDR2Test5.bdf" top-level design which contains an HPC1_example_top block generated from the HPC1_example_top.v verilog module generated by the Megawizard for the HPCII controller. I then placed pins in my design, ran the HPC1_pin_assignments.tcl, properly placed the pins in the design and tried to compile the design. I'm getting the below error message:

Error: Output port "O" of PSEUDO_DIFF_OUT primitive "HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1 _phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_pdiff" must drive only one OBUF primitive on the I port and cannot drive anything else

The RTL viewer shows that the low-level primitive in question IS only driving one other primitive so I'm lost. Other forum posts regarding this issue seem to have been resolved by renaming incorrectly named pin names but as far as I can see, my pins are named correctly accordingly to the HPC1_pin_assignments.tcl file.

As previously recommended in this forum, the negative pins of diff pairs have been left unconnected in the top-level design. The pin planner automatically assigned the negative pin location when I filled in the positive pin location.

I'm also getting an error message saying that the bidirectional mem_dqsn signals must be driven by a pin. But since the pin planner automatically assigns a negative pin with a different name I'm unable to do this. Would it work to change the I/O standard of diff pins to SSTL-18 CLASS I and instead manually assign the negative pin in the pin planner?

Any pointers in the right direction are appreciated!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Ok, I figured this out. The altera generated HPCII instance requires the DDR2 clock pins to be bidirectional. After changing this, the design compiles.

    Also, I found that the only way to properly use differential pins in my DIMM design, I had to:

    1) Temporarily change all Differential SSTL-18 I/O types in the tcl file to single-ended SSTL-18.

    2) Assign all differential pins one by one as single-ended in the pin planner. This has the effect that the pin planner does not try to automatically add an incorrectly named negative pin for the diff pair.

    3) Change the single ended SSTL-18 pins back to differential SSTL-18.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    After changing all diff signals to single ended I/O standard (SSTL-18) the errors were reduced from 28 to 2. Note that the first error is the same as before:

    Error: Output port "O" of PSEUDO_DIFF_OUT primitive "HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_pdiff" must drive only one OBUF primitive on the I port and cannot drive anything else

    Warning: PLL "HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_clk_reset:clk|HPC1_phy_alt_mem_phy_pll:half_rate.pll|altpll:altpll_component|altpll_quo3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected

    Error: Input port DATAIN of DDIO_IN primitive "HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_clk_reset:clk|ddio_mimic" must come from an I/O IBUF or DELAY_CHAIN primitive

    Note that these error/warning messages are very similar to these previously discussed below. Unfortunately, no clue was given to what was wrong.

    http://www.alteraforum.com/forum/archive/index.php/t-27313.html

    http://alteraforum.org/forum/showthread.php?p=109195

    I have attached the updated top-level BDF screenshot as well as the pin planner and assignment editor CSV files. I'm hoping someone can make sense of these errors...

    Thanks!