Output port "O" of PSEUDO_DIFF_OUT primitive... must drive only one OBUF primitive...

After changing all diff signals to single ended I/O standard (SSTL-18) the errors were reduced from 28 to 2. Note that the first error is the same as before:

Error: Output port "O" of PSEUDO_DIFF_OUT primitive "HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_pdiff" must drive only one OBUF primitive on the I port and cannot drive anything else

Warning: PLL "HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_clk_reset:clk|HPC1_phy_alt_mem_phy_pll:half_rate.pll|altpll:altpll_component|altpll_quo3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK[2] is not connected

Error: Input port DATAIN of DDIO_IN primitive "HPC1_example_top:inst1|HPC1:HPC1_inst|HPC1_controller_phy:HPC1_controller_phy_inst|HPC1_phy:HPC1_phy_inst|HPC1_phy_alt_mem_phy:HPC1_phy_alt_mem_phy_inst|HPC1_phy_alt_mem_phy_clk_reset:clk|ddio_mimic" must come from an I/O IBUF or DELAY_CHAIN primitive

Note that these error/warning messages are very similar to these previously discussed below. Unfortunately, no clue was given to what was wrong.

http://www.alteraforum.com/forum/archive/index.php/t-27313.html

http://alteraforum.org/forum/showthread.php?p=109195

I have attached the updated top-level BDF screenshot as well as the pin planner and assignment editor CSV files. I'm hoping someone can make sense of these errors...

Thanks!