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Honored ContributorOutput Pin Driving Another Output Pin
Hello all,
I've run into an unusual problem. I'll start off by describing my goal: I'm designing a circuit that can test for short circuits and open circuits in a wiring harness. The wiring harness does not have a CAN bus or anything complicated like that - just simple wires. Here's how it works I have two CPLDs, one as a designated driving end (all pins are output) and another as an receiving end (all pins are input). The driving end CPLD is programmed to be a Serial In Parallel Out shift register and the receiving end is a Parallel In Serial Out shift register. Let's assume all the wires in the harness are one-to-one i.e. no junctions. Let's also assume that there are only 8 wires. So, to test the first wire in the harness, the driving end register is loaded with 10000000. The receiving end also sees this and it all ends well. The driving end is then clocked and it reads 01000000. If the receiver also reads this, then that wire is OK. But suppose there is a short circuit between wire 2 and 3. If that's the case, then the receiving end will read 01100000. This, too, is OK as we have detected the short and can take action. But what happens at the driving end? The CPLD's pin 3 will be forcing 0V and pin 2 will be forcing 3.3V. The short circuit between pin 2 and 3 will result in two output pins connected together. I'm assume that a significant current will flow from pin 2 to pin 3 and damage could result. Note that the shift registers/CPLDs are being driven by a microcontroller. Also note that the harness is usually quite large, around 200-300 wires. Some of which are one-to-many connections. This is why a CPLD was an attractive option as it allows me to program a large shift register and allows testing of a large harness with a relatively small circuit. How can I handle such a problem?16 Replies
Altera_ForumIndeed the recommended solution would be using buffers. These will also help to protect CPLD pins from damage which is likely in case of such long wires possibly, shortcircuited and maybe subject to esd or other kind of electrical surges.
I'd use a transistor array, pull up resistors <=10k and I'd design the test cycle in order to minimize errors due to electrical coupling or emi (i.e. for the 3rd wire, test both with 00100000 and with 11011111 pattern)- Altera_Forum
I discussed this with my colleagues at work and they feel there a couple of limiting factors here. One of things that concern me is the fact most wiring harnesses are going to have some large junctions. Lets suppose we have two junctions with upto 20 wires going outward from both of them.
If there is a short circuit between the junctions, the CPLD's pin will need to drive as much as 40 wires. With a 5K pull down resistor, the current from the pin will be about 0.66mA at 3.3V. If, however, there is a junction of 40 wires the current is about 26.4mA - which exceeds the Max V absolute max. ratings (which aren't continuos anyway!). Is the answer to this problem reducing the speed of operating and using a larger resistor? A 47K resistor and a 100 wire junction will lead to a current of just 7mA. OR - should I just use a transistor array IC at the output of the Max V and use those to drive the wires - in essence, a buffer? - Altera_Forum
Thank you very much. The wires are quite long - upto 1.5m and can be longer if they're meant for trucks. So they will indeed act as an antenna, I reckon.
What value of resistance would you recommend in this case, for a pull down? Higher or lower than 5k? - Altera_Forum--- Quote Start --- If I understand your solution, it's as follows: Instead of outputting 01000000, I should instead output Z0ZZZZZZ, where Z symbolizes high impedance. The pull up resistors at the receiving end will then up the high impedance line to 3.3V. The receiver will therefore read: 10111111 If there is a short circuit between pin 2 and 3, then the receiver will read 10011111. But since the other pin is in high-impedance state, it will have no affect on the device. Do I understand you correctly? --- Quote End --- Perfect. You got it. Regarding internal pull ups, the problem is that 5k is the minimum but the actual resistance is not controlled and will be very different on each device. I don't have the MaxV datasheet here, but I guess you can easily expect values up to 20k. Anyway if you are sure your wires won't catch up a lot of emi, internal pull ups are fine. I will not reduce the clock speed, but I'd rather exploit the higher than required speed to multiple sampling the received signals and perform a digital filtering: this way you should prevent receive errors even more.
- Altera_Forum
If I understand your solution, it's as follows:
Instead of outputting 01000000, I should instead output Z0ZZZZZZ, where Z symbolizes high impedance. The pull up resistors at the receiving end will then up the high impedance line to 3.3V. The receiver will therefore read: 10111111 If there is a short circuit between pin 2 and 3, then the receiver will read 10011111. But since the other pin is in high-impedance state, it will have no affect on the device. Do I understand you correctly? Regarding, internal pull up resistors. The Max V handbook states that min. value at 3.3V VCCIO is 5k. Will this not be adequate? If using external resistors provide more reliable resistors then I'll prefer those. However, I should mention that the speed of operation is not very high. The receiving end shift register is clocked at only 62.5kHz and I could reduce it further still. Naturally, the driving end is even slower. Do you still reckon that external resistors will provide us with a better option? If so, what value would you recommend? Secondly, what if I instead use pull down resistors? This would be beneficial as the current layout is only two layer and the bottom layer is a Ground. I could connect the resistors using only a via. Obviously, I will have to output Z1ZZZZZZ instead of Z0ZZZZZZ. Thank you for an excellent solution, by the way. Also, how would it handle an open wire? Here's my understanding, if suppose wire 4 is open. The driving end outputs ZZZ0ZZZZ. The receiver should read 11101111 but instead it reads 11111111. From this we know that we have an open circuit at pin 4. Am I correct? - Altera_Forum
The common solution is pulling up all wires with resistors and then drive the target line low with an open drain output.
In the CPLD you'll program bidirectional I/Os. The data out signal should be hardwired to a low level and you control the output pin through the OE signal. If you don't want external resistors, you may use the internal pull up option, but I'd not recommend it if your wires are long: the built in pull ups are usually in the tens of kohm range and the signals can be affected by stray electrical noise.
