Honored Contributoroutput error clocks from PLL
HI! Everyone!
I met a strange question before. the source clock is 48Mhz, So I want to use a PLL to get c0(CLK_25MHz) and c1(CLK_100MHz).But when I use Modelsim and SIgnalTap II for verification,the result made me surprised.
The following is Modelsim simulation printscreen,I know It's right:
and this is the SignalTap II printscreen:
You can see the Duty Cycle is different, SO I wonfer what happened,can you tell me?
************************************************** **
PS: the following is my HDL source and testbench code:
HDL source code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY SYSTEM_CONTROL IS
PORT(--INPUT SIGNALS
CLK : IN STD_LOGIC; --FPAG输入时钟信号48MHz
RST_n : IN STD_LOGIC; --系统复位信号
--OUTPUT SIGNALS
SYS_RST_n: OUT STD_LOGIC; --系统全局复位信号，低有效
CLK_25M : OUT STD_LOGIC; --PLL输出25MHz时钟
CLK_100M : OUT STD_LOGIC --PLL输出100MHz时钟
);
END ENTITY SYSTEM_CONTROL;
ARCHITECTURE behave OF SYSTEM_CONTROL IS
SIGNAL LOCKED: STD_LOGIC; --PLL输出有效标志位，高表示PLL输出有效
SIGNAL PLL_RST: STD_LOGIC; --PLL复位信号，高有效
SIGNAL RST_r1: STD_LOGIC; --PLL复位寄存信号r1
SIGNAL RST_r2: STD_LOGIC; --PLL复位寄存信号r2
SIGNAL SYS_RST_nr0:STD_LOGIC; --全局系统复位寄存信号r0，低有效
SIGNAL SYS_RST_nr1: STD_LOGIC; --全局系统复位寄存信号r1，低有效
SIGNAL SYS_RST_nr2: STD_LOGIC; --全局系统复位寄存信号r2，低有效
SIGNAL CLK_100M_r: STD_LOGIC; --PLL输出100MHz时钟寄存信号
COMPONENT PLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
--***********************************************
--***********************************************
--PLL复位信号产生，高有效
--异步复位，同步释放
PROCESS(CLK,RST_n,RST_r1)
BEGIN
IF RST_n = '0' THEN
RST_R1 <= '1';
ELSE
IF CLK'EVENT AND CLK = '1' THEN
RST_r1 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST_n,RST_r2,RST_r1)
BEGIN
IF RST_n = '0' THEN
RST_r2 <= '1';
ELSE
IF CLK'EVENT AND CLK = '1' THEN
RST_r2 <= RST_r1;
END IF;
END IF;
END PROCESS;
PLL_RST <= RST_r2;
--***********************************************
--***********************************************
--系统复位全局信号产生，低有效
--异步复位，同步释放
SYS_RST_nr0 <= RST_n AND LOCKED; --系统复位直到PLL有效输出
PROCESS(CLK_100M_r,SYS_RST_nr0,SYS_RST_nr1)
BEGIN
IF SYS_RST_nr0 = '0' THEN
SYS_RST_nr1 <= '0';
ELSE
IF CLK_100M_r'EVENT AND CLK_100M_r = '1' THEN
SYS_RST_nr1 <= '1';
END IF;
END IF;
END PROCESS;
PROCESS(CLK_100M_r,SYS_RST_nr0,SYS_RST_nr2,SYS_RST _nr1)
BEGIN
IF SYS_RST_nr0 = '0' THEN
SYS_RST_nr2 <= '0';
ELSE
IF CLK_100M_r'EVENT AND CLK_100M_r = '1' THEN
SYS_RST_nr2 <= SYS_RST_nr1;
END IF;
END IF;
END PROCESS;
SYS_RST_n <= SYS_RST_nr2;
--***********************************************
--***********************************************
--例化PLL产生模块
PLL_inst : PLL PORT MAP
(
areset => PLL_RST, --PLL复位信号,高电平复位
inclk0 => CLK, --PLL输入时钟，25MHz
c0 => CLK_25M, --PLL输出25MHz时钟
c1 => CLK_100M_r, --PLL输出100MHz时钟
locked => LOCKED --PLL输出有效标志位，高表示PLL输出有效
);
CLK_100M <= CLK_100M_r;
END ARCHITECTURE behave;
*************************************************
Testbench code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY SYSTEM_CONTROL_vhd_tst IS
END SYSTEM_CONTROL_vhd_tst;
ARCHITECTURE SYSTEM_CONTROL_arch OF SYSTEM_CONTROL_vhd_tst IS
-- constants
CONSTANT CLK_PRD:TIME:= 21 NS; --the source clock is 48MHz
-- signals
SIGNAL CLK : STD_LOGIC;
SIGNAL CLK_25M : STD_LOGIC;
SIGNAL CLK_100M : STD_LOGIC;
SIGNAL RST_n : STD_LOGIC;
SIGNAL SYS_RST_n : STD_LOGIC;
COMPONENT SYSTEM_CONTROL
PORT (
CLK : IN STD_LOGIC;
CLK_25M : OUT STD_LOGIC;
CLK_100M : OUT STD_LOGIC;
RST_n : IN STD_LOGIC;
SYS_RST_n : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : SYSTEM_CONTROL
PORT MAP (
-- list connections between master ports and signals
CLK => CLK,
CLK_25M => CLK_25M,
CLK_100M => CLK_100M,
RST_n => RST_n,
SYS_RST_n => SYS_RST_n
);
CLK_init : PROCESS
-- variable declarations
BEGIN
CLK <= '1';
WAIT FOR CLK_PRD/2;
CLK <= '0';
WAIT FOR CLK_PRD/2;
END PROCESS CLK_init;
RST_n_INIT : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
RST_n <= '0';
WAIT FOR CLK_PRD*4;
RST_n <= '1';
WAIT;
END PROCESS RST_n_INIT;
END SYSTEM_CONTROL_arch;
