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Altera_Forum
Honored Contributor
Honored Contributoroutput error clocks from PLL
HI! Everyone! I met a strange question before. the source clock is 48Mhz, So I want to use a PLL to get c0(CLK_25MHz) and c1(CLK_100MHz).But when I use Modelsim and SIgnalTap II for verification,the...
Altera_ForumHonored Contributor
Honored ContributorHi,
SignalTap captures data on the sampling clk. Ideally you use same sampling clk as data clk, Or integer multiple of it since timing problems and cross domain issues apply to this tool as to logic. so I believe you are sampling your clk wrongly.
