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Altera_Forum
Honored Contributor
15 years agooutput error clocks from PLL
HI! Everyone! I met a strange question before. the source clock is 48Mhz, So I want to use a PLL to get c0(CLK_25MHz) and c1(CLK_100MHz).But when I use Modelsim and SIgnalTap II for verification,the...
Altera_Forum
Honored Contributor
15 years agoIn theory and as long as sampling clk is twice or more its data then it should be ok. i.e it does not need be integer strictly. In practice I always sample my data on its own clk and get more consistent results. I use several signaltap instants per file if required. I don't trust the signaltap clk domain cross over when data clk and sampling clk are not related.