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Altera_Forum's avatar
Altera_Forum
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15 years ago

output error clocks from PLL

HI! Everyone! I met a strange question before. the source clock is 48Mhz, So I want to use a PLL to get c0(CLK_25MHz) and c1(CLK_100MHz).But when I use Modelsim and SIgnalTap II for verification,the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

sampling clock must be equal to twice or more integer multiple of 100 and 25MHz otherwise you get timing problems in the signaltap buffer(as any dc fifo). Moreover you are violating sampling theorem (Nyquist will get angry??)