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Altera_Forum
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15 years ago

output error clocks from PLL

HI! Everyone! I met a strange question before. the source clock is 48Mhz, So I want to use a PLL to get c0(CLK_25MHz) and c1(CLK_100MHz).But when I use Modelsim and SIgnalTap II for verification,the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

kaz,

Thanks for your reply, In the Design, I used the ouput clcok c1(CLK_100MHz) to sample data, But the sampling clock I used in the SignalTap II is the source clock(48MHz), I can't understand If there is any relation between the two sampling clock used in different area, So Can you make it more clear,many thanks!