Honored ContributorHello,
Our FPGA is supplied by an external oscillator. It's an integrated, stable oscillator (not just a crystal or a RC circuit), at 80 MHz. Is it considered a good engineering practice to route it through a 1-to-1 PLL prior to using it as a clock in my design? Why? Thanks in advance
Honored ContributorIf your oscillator is of good quality (It sounds like your is) then you shouldn't need to route it through a PLL.
If the Oscillator is also used to clock input/output signals from the FPGA then routing through a PLL may cause you timing issues where by the internal clock is momentarily out of phase with the external clock.Honored ContributorHonored ContributorWhat I was trying to say was that the output of the PLL will not be identical to the input (Otherwise why put a PLL in?)
Jitter on the input will be filtered by the PLL (Depending on the bandwidth setting). So the output may appear jittered relative to the input. This may only be a small amount of jitter but there is a possibility of causing setup/hold violations.Honored ContributorCan you suggest when it's a good idea to do the routing of the clock through a PLL?
Honored ContributorTo my opinion, there's no benefit of PLL usage if no derived clocks (frequency or phase variation) are utilized. A PLL generally adds a considerable amount of jitter to a good standard quality crystal oscillator, if phase noise is critical for your application (e.g. when sourcing an ADC clock from FPGA in DSP applications) you should pay attention.
The capabilties of FPGA internal PLLs to improve the quality of a poor clock signal are rather limited in contrast. Furthermore, there's some risk of PLL loose of lock in applications with strong on-board interference sources, particularly with previous device families as Cyclone II. On the other hand, routing the clock to a dedicated input and providing all required PLL supply decoupling preserves any option to update the design to utilize PLLs.
