Oscillator through 1-to-1 PLL for clock

To my opinion, there's no benefit of PLL usage if no derived clocks (frequency or phase variation) are utilized. A PLL generally adds a considerable amount of jitter to a good standard quality crystal oscillator, if phase noise is critical for your application (e.g. when sourcing an ADC clock from FPGA in DSP applications) you should pay attention.

The capabilties of FPGA internal PLLs to improve the quality of a poor clock signal are rather limited in contrast.

Furthermore, there's some risk of PLL loose of lock in applications with strong on-board interference sources, particularly with previous device families as Cyclone II.

On the other hand, routing the clock to a dedicated input and providing all required PLL supply decoupling preserves any option to update the design to utilize PLLs.