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Altera_Forum
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16 years ago

Oscillator through 1-to-1 PLL for clock

Hello, Our FPGA is supplied by an external oscillator. It's an integrated, stable oscillator (not just a crystal or a RC circuit), at 80 MHz. Is it considered a good engineering practice t...
Altera_Forum's avatar
Altera_Forum
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16 years ago

What I was trying to say was that the output of the PLL will not be identical to the input (Otherwise why put a PLL in?)

Jitter on the input will be filtered by the PLL (Depending on the bandwidth setting). So the output may appear jittered relative to the input. This may only be a small amount of jitter but there is a possibility of causing setup/hold violations.