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Altera_Forum
Honored Contributor
Honored ContributorOscillator through 1-to-1 PLL for clock
Hello, Our FPGA is supplied by an external oscillator. It's an integrated, stable oscillator (not just a crystal or a RC circuit), at 80 MHz. Is it considered a good engineering practice t...
Altera_ForumHonored Contributor
Honored ContributorCan you suggest when it's a good idea to do the routing of the clock through a PLL?
