Optimal frequency selection for IOPLL's VCO: minimize or maximize?

@EngWei_O_Intel? Anyone?

Thanks,

-Roee

Hi,

Can you please provide example frequencies to replicate the behavior that you are observing in Stratix 10?

Regards

Hi @Ash_R_Intel, thanks for the response.

A simple example case is as the IOPLL IP generator GUI comes up by default: refclk 100 MHz, outclk0 100 MHz.

For reference, both Arria 10 and Stratix 10 in -1 speed grade have IOPLL VCO frequency operating ranges of 600 MHz min to 1600 MHz max.

So, based on the description given in the IOPLL IP generator GUI, we'd expect it to set the VCO frequency to 600 MHz (N=1, M=6, C0=6). And this is exactly what it does for an Arria 10 target, but not for a Stratix 10 target. For a Stratix 10 (-1 speed grade), it sets the VCO frequency to 1600 MHz (N=1, M=16, C0=16), which is opposite of what we'd expect.

Thanks,
-Roee

Hi Rooe,

Thanks for providing the examples.

I see the differences in the A10 and S10 PLL VCO frequencies.

Please note that, though the names sound same, the two devices have different components. IOPLL in A10 is also found in Cyclone 10 GX, but S10 IOPLL is unique to the device.

Are you facing any timing issues or functional issues due to the generated clock in S10 device?

I will take this observation to the engineering team for more clarifications.

Regards

Thanks, @Ash_R_Intel.

Yes, I'm aware that the S10 IOPLL is not identical to the A10/C10GX IOPLL. I only mentioned the latter for added context, but my question is specifically about the S10, where the S10 IOPLL IP generator is not self-consistent.

No, I'm not asking because of any particular timing or functional issue at this time. I'm developing a configurable generalized design that uses the S10 IOPLL, and so I want to make sure I capture the optimal configuration guidelines for my design's configuration matrix.

Thank you for taking the observed inconsistency in the S10 IOPLL IP generator to engineering for clarification. I'll look forward to hearing back from you.

Thanks,
-Roee

Hi @Ash_R_Intel,

I've not heard back from you. Have you gotten an answer from engineering?

Thanks,

-Roee

Hello roeekalinsky,

Thanks for your patience!!

The possible explanation that I received is that, S10 PLL is designed that way to get a better lock range compared to A10. The lock range of the PLL is determined by the following equations:

Fin(min) = Fvco(min) * N / M

Fin(max) = Fvco(max) * N / M

In Stratix 10, the algorithm does a better job to give +/- variance to the requested input clock frequency. That seems to be a reasonable trade-off compared to optimal jitter performance.

Hope that answer your query satisfactorily.

Regards

Hi @Ash_R_Intel,

Thank you for getting back to me, and that's interesting to know that the S10 is more tolerant than A10 of Fin variation. But I don't think that actually answers my question.

The original question remains as follows:

With the S10 IOPLL, for a given configuration, is the intended guideline to minimize or to maximize the VCO frequency?

Or in other words, with the S10 IOPLL, is it recommended to select the lowest possible M or the highest possible M for a given frequency range specification?

Or in other words yet, using the example I provided with Fin = Fout = 100 MHz, is it better to select:

A) minimize: N=1, M=6, C0=6, Fvco = 600 MHz

or:

B) maximize: N=1, M=16, C0=16, Fvco = 1600 MHz

or maybe even something in between:

C) middle: N=1, M=11, C0=11, Fvco = 1100 MHz?

The S10 IOPLL IP wizard says (A) but does (B), so something's awry. Hence the original question. Please clarify which was intended, (A) or (B)? And why? That will answer my original question.

And then, your comments on lock range actually seem to suggest that (C) may be preferred over (A) or (B), as that would maximize the available lock range +/- frequency tolerance by centering Fvco, and not being right up against either frequency limit. Is that a correct interpretation?

Thanks,
-Roee

Hi,

The decision to select VCO frequency by the user can be based on the following statement:

"The smallest phase shift is determined by the VCO period divided by eight (for I/O PLL)."

Reference: https://www.intel.com/content/www/us/en/programmable/documentation/mcn1440569668630.html#fnsrc_4

Regards

Hi @Ash_R_Intel ,

Again thank you for this additional tip, but it still doesn't actually answer my question. I'm aware of the relationship between Fvco and phase shift resolution, but I'm not doing any phase shifting here, so this is a non-factor.

Are you able to answer my original question?

Thanks,
-Roee