EngWei_O_IntelFrequent ContributorJoined 5 years ago435 Posts28 LikesLikes received34 SolutionsView All Badges
ContributionsMost RecentMost LikesSolutionsRe: Rd, OCT Default Value in LVDS Hi there I am not fully confirm about its appearance in any viewer. But the setting shall be visible in fitter report. Thanks. Eng Wei Re: Rd, OCT Default Value in LVDS Hi there By checking on https://www.intel.com/content/www/us/en/programmable/documentation/sam1403483633377.html#sam1403482197912 The Rd OCT shall be of 100 ohm. Re: DDR output buffer and LVDS pins Hi there You may refer to link below to better understanding the implementation and design guideline of clock gating. Recommended Design Practices, Quartus II Handbook (intel.com) Thanks. Re: Rd, OCT Default Value in LVDS Hi Rich If you refer to https://www.intel.com/content/www/us/en/programmable/documentation/nik1398707230472.html parameter is meant for usage of transceiver. For LVDS GPIO, you can do the setting through Assignment Editor, or manually using the INPUT_TERMINATION assignment as mentioned in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl-pro-qsf-reference.pdf Thanks. Re: Product Hi there We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: arria10 maximum current consumption Hi there EPE is the correct tools. Referring to documentation below: https://www.intel.com/content/www/us/en/programmable/documentation/mhi1422370348549.html#mhi142230078451 You can view the various current spec in the report tab, which I glance thru it and quick check the Total current is in mA range. Thanks. Re: how to achieve 4 channel LVDS ADC read Hi there Since the LVDS support up to deserialization factor of 10, you can refer to link below to compute for other factors: https://www.youtube.com/watch?v=02lgfcxSjQA For the spec you mentioned, Cyclone IV shall be supported. Thanks. Re: ALTLVDS_RX Hi There are benefits over multipoint application for using BLVDS: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii51008.pdf#page=8 I crossed check the "High-Speed Differential Interfaces" section in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii51001.pdf and Table 1–31 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf The max data rate shall be 740 Mbps with freq of 370MHz if you are using Cyclone III LS device C7, I7 grade depending on the mode. Thanks. Re: ALTLVDS_RX Hi Can you help me with following? 1. Which part of the datasheet doc you are referring to when you mentioned it is not recommended to use ALTLVDS IP? We can help to check if our interpretation is aligned. 2. When you mentioned that the de-serializer fails to find signals, do you mean the inputs are not toggling or the output is incorrect? The data rate is limited by the IO specification per device family which we need to adhere to. By using the IP, you will be able to directly utilizing multiple capabilities that come together with it, which you will need to build it with manual logic coding. Thanks. Re: BemicroMAX 10 ADC Hi there We don't have insight on how the connection been decided and what characterization had been carried out on 3rd party's Evaluation board. Can you check directly with the vendor on the board connection? Thanks. Eng Wei