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Benjamin182's avatar
Benjamin182
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4 years ago

DDR output buffer and LVDS pins

Hi guys, I've got a question. I need to output a gated LVDS clock (I know gated clocks are bad). On my MAX10 FPGA, I was planning on using a DDR buffer configured like this ddr_output_DUMMY : d...
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    Benjamin182
    Icon for New Contributor rankNew Contributor
    4 years ago

    Thanks for the reply, but the clock needs to be output from the FPGA to an ADC. And the clock needs to be gated, that's how the ADC is designed.

    https://www.analog.com/en/products/ad7961.html

    How should I do it with a Max 10 FPGA?