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roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
4 years ago

Optimal frequency selection for IOPLL's VCO: minimize or maximize?

Is best IOPLL performance obtained by minimizing the VCO frequency, or maximizing it? The IOPLL IP generator GUI appears to be confused on this issue, at least for Stratix 10. It describes one thin...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello roeekalinsky,

Thanks for your patience!!

The possible explanation that I received is that, S10 PLL is designed that way to get a better lock range compared to A10. The lock range of the PLL is determined by the following equations:

Fin(min) = Fvco(min) * N / M

Fin(max) = Fvco(max) * N / M


In Stratix 10, the algorithm does a better job to give +/- variance to the requested input clock frequency. That seems to be a reasonable trade-off compared to optimal jitter performance.


Hope that answer your query satisfactorily.


Regards