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Altera_Forum's avatar
Altera_Forum
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11 years ago

Optical Transceiver interfacing problem in stratix-V FPGA

Hello,I'm facing problem while interfacing optical transceiver of stratix-V FPGA based board with Xilinx based FPGA board.In both sides i'm using optical transceivers with sFPDP protocol at 6.25 Ghz rate.I'm able to transmit and receive between two FPGAs of same family(i.e Altera or Xilinx).I've performed the loopback test for each FPGAs also and it is also working fine.

But when i'm trying to connect the Stratix-v based FPGA board and Xilinx based FPGA board i'm not able to receive any data.The sFPDP parameters on both the side are same,but i've doubt on the transceiver paramters.

Hereby I'm attaching the transceiver settings files of both the FPGAs.Anyone plz help me.

Thanks you,

Mohan V.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    When you refer to cannot receive any data, is it that bit error observed or nothing at all? You can try to play around with the Stratix V PMA settings to see if can improve the situation if it is signal integrity issue.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    In my previous thread I mentioned can't received the data means I'm not receiving any data,it's simply coming zeros.iIn my old thread I've attached the transceiver parameters settings of both FPGAs.Can u tell me any differences in the PMA settings in both the files..

    Thank u.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi Mohanvinnakota,

    When you mentioned a loopback in the FPGA do you mean a "loopback within the FPGA" or "loopback from FPGA to SFP and back to FPGA"? This will be helpful to check the PMA setting as well.

    When you mentioned there is no signal was the rxlockedtodata or the rxcdrlock asserted?

    I would still suggest to use the scope to narrow down the root cause here. It will be faster to see where the signal was loss.