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Honored Contributor
Honored ContributorOptical Transceiver interfacing problem in stratix-V FPGA
Hello,I'm facing problem while interfacing optical transceiver of stratix-V FPGA based board with Xilinx based FPGA board.In both sides i'm using optical transceivers with sFPDP protocol at 6.25 Ghz...
Altera_ForumHonored Contributor
Honored ContributorHi Mohanvinnakota,
When you mentioned a loopback in the FPGA do you mean a "loopback within the FPGA" or "loopback from FPGA to SFP and back to FPGA"? This will be helpful to check the PMA setting as well. When you mentioned there is no signal was the rxlockedtodata or the rxcdrlock asserted? I would still suggest to use the scope to narrow down the root cause here. It will be faster to see where the signal was loss.
