Honored ContributorHello guys !!
I have a little question.. I'm using some vhdl objects in a schematic (.bdf) file. Now I want to add some leading zeroes to a bus eg: mybus[13..0] -> [0 0 mybus] In VHDL this is operation is straightforward but how can I get the same result in a .bdf file ?? Thank you for help !! Have a nice day !
Honored ContributorEasiest to use named association.
Label the input to the VHDL as mybus. Do not connect it to anything. connect a bus to GND. label the bus mybus[13..12] connect the other part to the signal of interest, label is mybus[11..0] Any reason you are using schematic and not VHDL?Honored ContributorThank you tricky, so I was doing it the right way. But it's a little annoying !
I'm using a schematic because it's a pretty large system and I use some standard cores in it (fir, comparator,mux etc etc). So because setting the cores using a schematic is simpler then doing it by hand in vhdl I use a mixed system. Probably there is a better way but as I still don't know it I'm working this way.. Do you have any suggestions ??Honored ContributorAll the standard cores generated from the megawizard generate VHDL/verilog components you can copy/paste into your VHDL. These are wrappers around the base component with all the generics set. You just need to map the ports.
Honored ContributorThank you Tricky.
So if I generate eg: parallel_add0.qip, I can use it in my VHDL top design using simply the direct instantiation? eg: my_parall_add0_inst : parallel_add0 PORT MAP(......) Your help is really appreciated ! Have a nice day !Honored ContributorIf you generated the core, and have a generated .vhd file, then yes, you can use direct instantiation.
