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Honored ContributorOn Adding leading zeros on a bus in a schematic (.bdf) file
Hello guys !! I have a little question.. I'm using some vhdl objects in a schematic (.bdf) file. Now I want to add some leading zeroes to a bus eg: mybus[13..0] -> [0 0 mybus] In VHD...
Altera_ForumHonored Contributor
Honored ContributorAll the standard cores generated from the megawizard generate VHDL/verilog components you can copy/paste into your VHDL. These are wrappers around the base component with all the generics set. You just need to map the ports.
