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Honored Contributor
Honored ContributorOn Adding leading zeros on a bus in a schematic (.bdf) file
Hello guys !! I have a little question.. I'm using some vhdl objects in a schematic (.bdf) file. Now I want to add some leading zeroes to a bus eg: mybus[13..0] -> [0 0 mybus] In VHD...
Altera_ForumHonored Contributor
Honored ContributorThank you Tricky.
So if I generate eg: parallel_add0.qip, I can use it in my VHDL top design using simply the direct instantiation? eg: my_parall_add0_inst : parallel_add0 PORT MAP(......) Your help is really appreciated ! Have a nice day !
