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TakaU's avatar
TakaU
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1 year ago

NIOSV on DK-SI-AGI027FA KIT Fail elf file download

I am try to implement NIOSV on DK-SI-AGI027FA KIT ( FPGA Devie is AGIB027R31B1E1V).
(HW part)
Top verilog file is copied form example golden_top design, and only use 100MHz clock
(other pins are commented out) and NIOS V are instantiated from NIOS V example design like
qsys_top u0 ( .clk_clk (clk_gpio_p_4), // input, width = 1, clk.clk
.pio_0_external_connection_export (out_data) // output, width = 4,);
(SW part)
This FPGA design are compiled successfully and sof file can be downloaded to DK-SI-AGI027FA KIT.Very basic program like "Hello C" program and BSP are build successful and .elf file are created. I tried to download .elf file then i got error message (see attached txt file)
Any advice are appreciated
and if someone tell me some good example about NIOSV on DK-SI-AGI027FA KIT ,
that is very helpful.
Thanks in advance
Configuration

2 Replies

  • TakaU's avatar
    TakaU
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi, let me post what i fix this.
    Since Freq. of clk_gpio_p_4 is 100MHz, I made 50MHz CPU clock from clk_gpio_p_4,
    and add some changes, elf file can be downloaded properly.

    Sorry for i posted my faults.

    Please close this.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    HI


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



    Regards

    Jingyang, Teh