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Altera_Forum
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13 years ago

NIOS & usage of DMA to transfer data between dual port memory and DDR2

Dear All,

in my NIOS application, once every 300ms I need to 'load' data from the on-chip FPGA memory, realised as dual-port memory, into the DDR2 memory, which

is used to run my NIOS application. All that because I need to prepare a data to be sent over the ethernet (using TSE + NicheStack).

The amount of data is not huge:8192x32, and so far I'm reading them using standard avalon interface and IORD_32DIRECT. By measurements on oscilloscope, the

transport of these data takes from 60-100ms, depending of whether there is another IRQ coming into my read loop or not.

I've realised that this takes too long, providing that my FPGA code can easily run with 200MHz clock, the IORD can fetch the data only using equivalent of roughly 5us clock(!!), some 130kHz!

So I was thinking to use DMA to run it. But I'm not sure how to connect it between my application DDR2 and avalon. Could someone enlighten me how to do it?

To bring my application to life I've used a simple socket server application coming with 3C120 development kit. Looking how they connect SGDMA between DDR2 and TSE, they use clock crossing bridge + avalon MM pipeline bridge + DDR2 SDRAM controller to connect to write descriptor of the SGDMA. On read descriptor side they use the same model, only in addition they connect to onchip-ram through pipeline bridge for descriptor memory.

Why there is a pipeline bridge in between? It seems that I miss some basics of working with DMA

thanks a lot

d.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    The pipeline bridges aren't always necessary. They are usually added to add some pipeline levels so improve timing. When you have a lot of masters connected to the same slave, the arbitration logic can add too many combinatorial levels and severly impact the FMax. By using pipeline bridges you reduce that complexity and are able to increase the FMax, at the cost of a higher latency.

    You can start by directly connecting your new DMA to the memories, and if you have a time failure, go in Timequest, try to identify the most critical paths and add pipeline bridges there to correct the timing violations.