Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorNewbie Verilog Math Q
From my reading, it appears that a register is a 2s complement signed value. Is this correct?
In other words, is the following accurate (please correct if not): reg [31:0] reg1; reg [31:0] reg2; If reg1 = FFFFFFFF and reg2 = 2, is the value of reg1+reg2 = 1 Thanks, in advance, ME4 Replies
Altera_ForumThe result 1 is correct.
Anyway the interpretation of register content as a 2-complement signed value or rather a unsigned value is a matter of your system. Please note that the above result also applies to a sum involving unsigned values, generating overflow.- Altera_Forum
Thanks Chris....
One q regarding the statement, "Anyway the interpretation of register content as a 2-complement signed value or rather a unsigned value is a matter of your system." Does this mean that I can select registers as signed/unsigned in Quartus. Or are you referring to my specific implementation? Could I bother you to elaborate? ME - Altera_Forum--- Quote Start --- Does this mean that I can select registers as signed/unsigned in Quartus. Or are you referring to my specific implementation? --- Quote End --- You simply define a reg: its content can be signed, unsigned, fractional, floating point or whatever you need. Verilog doesn't bother about register content: it's up to you the correct interpretation. Clearly, the basic adder works for both signed (2-compl), unsigned and fixed point values. If you want to sum 2 floats you need a specific adder module.
- Altera_Forum
Thanks much. After a little more RTFM, it looks like:
reg [31:0] reg1 is unsigned reg signed [31:0] reg 2 is signed Learning on the fly is always fun..... Thnx again..
