Newbie Verilog Math Q

The result 1 is correct.

Anyway the interpretation of register content as a 2-complement signed value or rather a unsigned value is a matter of your system.

Please note that the above result also applies to a sum involving unsigned values, generating overflow.

Thanks Chris....

One q regarding the statement, "Anyway the interpretation of register content as a 2-complement signed value or rather a unsigned value is a matter of your system."

Does this mean that I can select registers as signed/unsigned in Quartus. Or are you referring to my specific implementation? Could I bother you to elaborate?

ME

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Does this mean that I can select registers as signed/unsigned in Quartus. Or are you referring to my specific implementation?

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You simply define a reg: its content can be signed, unsigned, fractional, floating point or whatever you need. Verilog doesn't bother about register content: it's up to you the correct interpretation.

Clearly, the basic adder works for both signed (2-compl), unsigned and fixed point values. If you want to sum 2 floats you need a specific adder module.

Thanks much. After a little more RTFM, it looks like:

reg [31:0] reg1 is unsigned

reg signed [31:0] reg 2 is signed

Learning on the fly is always fun.....

Thnx again..