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Honored Contributor
Honored ContributorNewbie Verilog Math Q
From my reading, it appears that a register is a 2s complement signed value. Is this correct? In other words, is the following accurate (please correct if not): reg [31:0] reg1; reg [31...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Does this mean that I can select registers as signed/unsigned in Quartus. Or are you referring to my specific implementation? --- Quote End --- You simply define a reg: its content can be signed, unsigned, fractional, floating point or whatever you need. Verilog doesn't bother about register content: it's up to you the correct interpretation. Clearly, the basic adder works for both signed (2-compl), unsigned and fixed point values. If you want to sum 2 floats you need a specific adder module.
