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Altera_Forum
Honored Contributor
Honored ContributorNewbie Verilog Math Q
From my reading, it appears that a register is a 2s complement signed value. Is this correct? In other words, is the following accurate (please correct if not): reg [31:0] reg1; reg [31...
Altera_ForumHonored Contributor
Honored ContributorThe result 1 is correct.
Anyway the interpretation of register content as a 2-complement signed value or rather a unsigned value is a matter of your system. Please note that the above result also applies to a sum involving unsigned values, generating overflow.
